|
A FPGA board with two cores, MAX
and FLEX, executes data transmission and stimulation. MAX core
generates stimulation data packets, inserts a cluster's address,
computes CRC and sends a stimulation frame to FLEX core. MAX core
receives stimulation, routes data to the addressed cluster, checks CRC,
handles wireless communication protocol.
|
Data communication
protocol simulation:
|
Loading data to stimulator
controller logic drivers and stimulation simulation:
|
|
| A master controller
that handles the wireless data link, network layer and routes the
stimulation data to an addressed cluster for stimulation.
|
|
 |
A stimulator
controller logic that controls a retina micro-stimulator. It is
scalable by either connects in a long chain and/or groups into
clusters.
It controls a digital to analog convert (DAC) to generate different
amplitudes of cathodic and anodic phases in a biphasic waveform.
Variable pulse widths of anodic, cathodic and interphase are also
adjustable in real time by this controller's built-in timer.
|
|
|
|